1. Field of the Invention
The present invention relates to a Digital-to-Analog (D/A) conversion and more particularly, to a D/A conversion method and a D/A converter designed for this method, in which Pulse Width Modulation (PWM) is used.
2. Description of the Prior Art
FIG. 1 schematically shows a conventional D/A converter, which is comprised of a Pulse Width Modulator (PWM) circuit 102, a latch circuit 104, and a Low-Pass Filter (LPF) circuit 105.
A digital input signal S.sub.IN is applied to the PWM circuit 102. The input signal S.sub.IN is a stream of coding pulses produced by modulating or encoding an original analog input signal according to Pulse Code Modulation (PCM). In other words, the input signal S.sub.In is a stream of Pulse-Code-Modulated (PCM) pulses.
The PWM circuit 102 receives the digital input signal S.sub.IN through an input terminal T1. The PWM circuit 102 modulates the PCM input signal S.sub.IN to produce a modulated output signal S.sub.PWM having a variable pulse width proportional to the amplitude of the input signal S.sub.IN. The modulated output signal S.sub.PWM is applied to the latch circuit 104.
The latch circuit 104 is formed by a Complementary Metal-Oxide-Semiconductor (CMOS) inverter comprising p- and n-channel MOS Field_effect Transistors (MOSFETs) M1 and M2. Gates of the MOSFETs M1 and M2 are coupled together to be connected to the output terminal of the PWM circuit 102. A source of the n-channel MOSFET M2 is connected to the ground. A source of the p-channel MOSFET M1 is connected to a power supply line applied with a power supply voltage V.sub.SS. Drains of the MOSFETs M1 and M2 are coupled together to be connected to an input terminal of the LPF circuit 105.
When the PWM output signal S.sub.PWM is in the logic high (H) level, the modulated output signal S.sub.LC of the latch circuit 104 is in the logic low (L) level. Thus, the output signal S.sub.LC is equal to zero or the ground voltage. When the PWM output signal S.sub.PWM is i the logic L level, the output signal S.sub.LC of the latch circuit 104 is in the logic H level. Thus, the output signal S.sub.LC is equal to the power supply voltage V.sub.SS.
The LPF circuit 105 receives the output signal S.sub.LC of the latch circuit 104 and removes its high-frequency components, thereby producing a smooth continuous analog output signal S.sub.OUT at an output terminal T2. The analog output signal S.sub.OUT is a same as the original analog input signal.
With the conventional D/A converter described above, when the maximum pulse width of each sample of the input signal S.sub.IN is W.sub.S, the sampling frequency is f.sub.S, and the pulse voltage of each sample is V.sub.P, the maximum voltage V.sub.MOUT of the analog output signal S.sub.OUT is given as EQU V.sub.MOUT =k.times.W.sub.S.times.V.sub.P, (1)
where k is a constant.
Therefore, to increase the maximum voltage V.sub.MOUT of the analog output signal S.sub.OUT, the pulse voltage V.sub.P of each sample needs to be increased.
Also, when the PCM input signal S.sub.IN is an n-bit signal (n is a natural number) and the PWM circuit 102 is formed by a counter operated at a frequency f.sub.c, the clock frequency f.sub.c of the counter is expressed as EQU f.sub.c =f.sub.S.times.2.sup.n (2)
This means that the clock frequency f.sub.c of the counter needs to be 2.sup.n times as large as the sampling frequency f.sub.S . In this case, the magnitude M.sub.QS of the quantization step of each sample is given as EQU M.sub.QS =k.times.W.sub.S.times.V.sub.P.times.(f.sub.S /f.sub.c) (3)
Thus, if the clock frequency f.sub.c of the counter is fixed and the sampling frequency f.sub.S is unchanged, the maximum voltage V.sub.MOUT of the analog output signal S.sub.OUT increases with the increasing voltage V.sub.P. In this case, however, there arises a disadvantage that the magnitude M.sub.QS of the quantization step of each sample also becomes larger with the increasing pulse voltage V.sub.P.
Moreover, if the original analog signal has the highest frequency f.sub.0, the highest frequency f.sub.0 satisfies the following relationship due to the sampling theorem. EQU 2f.sub.0.ltoreq.f.sub.S (4)
Therefore, from the above equation (2) and the above inequality (4), the clock frequency f.sub.c of the counter satisfies the following inequality (5). EQU 2.times.f.sub.0.times.2.sup.n.ltoreq.f.sub.c (5)
It is seen from the inequality (5) that the clock frequency f.sub.c of the counter has the minimum value of (2.times.f.sub.0.times.2.sup.n). Accordingly, there arises a disadvantage that the latch circuit 104 serving as an output circuit is required to have a switching speed corresponding to the clock signal with a frequency as high as (2.times.f.sub.0.times.2.sup.n) or higher.
Additionally, the signal-to-noise ratio (S/N) for a linear- or uniform-quantized PCM signal is given by EQU S/N=1.7+6B, (6)
where B is the number of quantization bits of the PCM signal. Therefore, the S/N of the PCM signal degrades with its decreasing level due to quantization noise. If the number B of the quantization bits is increased to improve the S/N, the total amount of information to be transmitted is increased.
Thus, to improve the S/N of the PCM signal without increasing the total amount of information to be transmitted, there have been developed and practically used the logarithmic compression codes termed ".mu.-law" and "A-law".
The logarithmic compression code ".mu.-law" is a 8-bit PCM code having first to eighth bits. The full-scale amplitude of the original analog signal is divided into 15 equal segments to form 16 steps. Each of the segments thus formed is linear- or uniform-quantized to form 16 equal quantization steps. The first bit, i.e., the Most Significant Bit (MSB), of the .mu.-law code is a sign bit to represent the polarity of the original analog signal. The second to fourth bits of the .mu.-law code are segment bits to designate one of the 16 segments. The fifth to eighth bits of the .mu.-law code are step bits to designate one of the 16 quantization steps for a corresponding one of the 16 segments.
The logarithmic compression code "A-law" also is a 8-bit PCM code having first to eighth bits. The full-scale amplitude of the original analog signal is divided into 13 equal segments to form 14 steps. Each of the segments thus formed is linear- or uniform-quantized to form 16 equal quantization steps. The first bit, i.e., the Most Significant Bit (MSB), of the A-law code is a sign bit to represent the polarity of the original analog signal. The second to fourth bits of the A-law code are segment bits to designate one of the 14 segments. The fifth to eighth bits of the A-law code are step bits to designate one of the 16 quantization steps for a corresponding one of the 14 segments.
With the conventional D/A converter shown in FIG. 1, however, there are the following problems.
First, the maximum pulse width of the PWM signal S.sub.PWM is determined by the sampling frequency f.sub.S. Therefore, to improve the pulse-width resolution of the PWM signal S.sub.PWM, the clock frequency f.sub.c of the counter serving as the PWM circuit 102, which determines the step number of the variable pulse width of the PWM signal S.sub.PWM, needs to be raised. In this case, however, there arises a problem that the relating hardware is required to operate at a higher speed and the power consumption is increased.
If the voltage or amplitude of the PWM signal S.sub.PWM is increased in order to expand the dynamic range of the analog output signal S.sub.OUT, the quantization step is increased and as a result, the minimum level of the output signal S.sub.OUT becomes higher according to the increased quantization step. Therefore, in this case also, the clock frequency f.sub.c of the counter serving as the SWM circuit 102 needs to be raised for reduction of the quantization step. Thus, there arises the same problem as above.
Second, there is a problem that the highest switching speed of the latch circuit 104, which allows the clock frequency f.sub.c of the counter having the minimum value of (2.times.f.sub.o.times.2.sup.n) to be inputted, limits the highest frequency f.sub.o of the applicable original analog signal.
Third, when the rotation of a motor is controlled by the use of the PWM signal S.sub.PWM, there is a problem that an uneven rotation of the motor occurs at a low duty of the signal S.sub.PWM. The uneven rotation is not completely removed, because the analog output signal S.sub.OUT contains some ripple at a low duty of the signal S.sub.PWM even after a averaging or smoothing operation by the LPF circuit 105.
Fourth, if the applied PCM signal S.sub.IN is linearly or uniformly quantized, the quantization noise becomes large at the low level of the signal S.sub.IN. If the bit number of the PCM signal S.sub.IN is increased to suppress the quantization noise, there arises a problem that the total amount of information or data to be transmitted is increased and at the same time, the clock frequency f.sub.c of the counter serving as the PWM circuit 102 needs to be raised. This problem is solved by the use of the above-described logarithmic compression codes termed ".mu.-law" and "A-law". However, in this case, there arises another problem that a conversion operation to convert the uniformly quantized PCM signal S.sub.IN to a logarithmically quantized one is required.
On the other hand, a PWM signal generator circuit applicable to speed or phase control of a motor in a Video Tape Recorder (VTR) is disclosed in the Japanese Non-Examined Patent Publication No. 4-192723 published in July 1992.
In this conventional PWM signal generator circuit, a PWM output signal with a variable pulse width according to an applied digital signal is produced. The PWM output signal has a first voltage corresponding to the logic high (H) level or a second voltage corresponding to the logic low (L) level. Each of the first and second voltages may have two or more different values.
With the conventional PWM signal generator circuit disclosed in the Japanese Non-Examined Patent Publication No. 4-192723, the output voltage range is expanded and the uneven rotation is suppressed due to resolution improvement of the PWM output signal. However, there is a problem that the uneven rotation of the motor is not satisfactorily reduced.